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? data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7771 features ? self-contained 3-phase motor controller ? operates as current or voltage controller ? 1, 3 or 10 amp output current ? 1.5% linearity ? 3% current regulating accuracy ? user-programmable compensation ? 10 khz - 100 khz pwm frequency ? complementary four-quadrant operation ? holding torque through zero current ? cycle-by-cycle current limit ? optional radiation tolerance to 100krads (see pw-82520r data sheet) pw-82520/21n 3-phase dc motor torque controller description the pw-82520n (100vdc) and pw-82521n (200vdc) are high performance current regulating torque loop controllers designed to accurately regulate the current in the motor windings of 3-phase brushless dc and brush dc motors. the pw-82520/21n is a completely self-contained motor controller that converts an analog input command signal into motor current and uses the signals from hall-effect sensors in the motor to commutate the current in the motor windings. the motor current is internally sensed and processed into an analog signal. the current signal is summed together with the command signal to produce an error signal that controls the pulse width modulation (pwm) duty cycle of the output, thus controlling the motor current. the pw-82520/21n perfor - mance can be tuned by utilizing the internal error amplifier and the external proportional/integral (pi) regulator network components to match motor characteristics. applications the pw-82520/21n is ideal for applications requiring current regula - tion and/or holding torque at zero input command. system applications include: pumps, actuators, antenna position, environmental control, reaction/momentum wheel systems using brushless and brush motors, flight surface control on aircrafts for horizontal stabilizers and flaps, missile fin control, fuel and hydraulic pumps, radar, and counter measure systems. packaged in a small dip-style hybrid package, the pw-82520/21n is well suited for applications with limited printed circuit board area. ? 2001 data device corporation make sure the next card you purchase has...
2 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 drive a drive b drive current c phase a phase a phase b phase b phase c phase c vbus+ a pwm logic circuitry commutation logic ha hb hc 5.0v 10k 10k 10k vbus? rsense pwm in + + 10.0k 5.0v error amplifier 100 - - + - + + amp command buffer 100 50k 50k 50k 50k hall a command out command in - command in + enable v dd supply gnd v ee pwm out command gnd v cc +5v error amp out error amp in current monitor out r s + hall b hall c case gnd +15v sync in v dr tach out case vbus+ c vbus+ b v cc rtn +5v rtn dir out 470pf figure 1. pw-82520/21n block diagram
3 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 table 1. pw-82520/21n absolute maximum ratings (t c = +25c unless ot h erwise specified) a a a ma ? ? ? ppm/c v 1 3 1.8 +20 0.055 0.100 0.080 330 1.5 1.5 1.3 -20 pulse width 50sec figure 7, v c m d = 0v +25c +125c +25c i d = 1a output (pw-82520n1) output current continuous output current pulsed current limit current offset output on-resistance output conductor resistance output conductor resistance temp coefficient diode forward voltage drop i o c i o p i c l i o f f s e t r o n r c v f parameter symbol value units command input + continuous output current pw-82520n1 pw-82520n3 pw-82520n0 / pw-82521n0 -5v to -15v +5v s upply +5v to +15v +15v s upply b us v oltage pw-82520n / (pw-82521n) i o c i o c i o c v e e v c c v d d v d r 15.0 1 3 10 -17.5 +5.5 +17.5 +17.5 100.0 (200.0) vdc a a a vdc vdc vdc vdc table 2. pw-82520/21n specifications (unless ot h erwise specified , v bus = 28v dc , v d r = +15v, v c c = +5v, v d d = +5v, v e e = -5v, t c = 25c, ll = 500 h , pwm i n = pwm out at ? f ree r unning freq uency) parameter symbol test conditions min typ max units peak output current (pulsed t = 50 s) pw-82520n1 pw-82520n3 pw-82520n0 / pw-82521n0 i o p i o p i o p 3 8 18 a a a command input - v c m d - 15.0 vdc logic inputs: enable , sync in, ha, hb, hc, error amp in, pwm in v ih 7.0 vdc vbus+ a,b,c vdc vbus- to gnd voltage differential v g n d d i f 0-v d d +1.0 vdc v c m d + tac h out / dir out v o h 40 vdc tac h out / dir out i o l 10 ma i o c i o p i c l i o f f s e t r o n r c v f output (pw-82520n0) output current continuous output current pulsed current limit current offset output on-resistance output conductor resistance output conductor resistance temp coefficient diode forward voltage drop pulse width 50sec figure 7, v c m d = 0v +25c +125c +25c i d = 10a 12.0 -100 14.0 0 10 18 15.4 +100 0.055 0.100 0.080 330 1.9 a a a ma ? ? ? ppm/c v i o c i o p i c l i o f f s e t r o n r c v f output (pw-82520n3) output current continuous output current pulsed current limit current offset output on-resistance output conductor resistance output conductor resistance temp coefficient diode forward voltage drop pulse width 50sec figure 7, v c m d = 0v +25c +125c +25c i d = 3a 3.4 -20 4 3 8 4.5 +20 0.055 0.100 0.080 330 1.8 a a a ma ? ? ? ppm/c v
4 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 table 2. pw-82520/21n specifications ( continued) (unless ot h erwise specified , v bus = 28v dc , v d r = +15v, v c c = +5v, v d d = +5v, v e e = -5v, t c = 25c, l l = 500 h , pwm in = pwm out at ? f ree r unning freq uency) parameter symbol test conditions min typ max units current monitor amp ( pw-82520n1/n3/n0, pw-82521n0 ) current monitor offset output current output resistance r o u t io c = 0a -10 -10 +10 +10 1 mvdc ma ? propagation delay td (on) td (off) from 1.5v on enable to 90% of vbus from 3.5v on enable to 10% of vbus 40 20 s s switch ing ch aracteristics pw-82520n1 upper drive turn-on rise time turn-off fall time lower drive turn-on rise time turn-off fall time pw-82520n3 upper drive turn-on rise time turn-off fall time lower drive turn-on rise time turn-off fall time pw-82520n0/21n0 upper drive turn-on rise time turn-off fall time lower drive turn-on rise time turn-off fall time t r t f t r t f t r t f t r t f t r t f t r t f rise time = 90% to 10% of v b u s fall time = 10% to 90% of v b u s i o = 1a rise time = 90% to 10% of v b u s fall time = 10% to 90% of v b u s i o = 3a rise time = 90% to 10% of v b u s fall time = 10% to 90% of v b u s i o = 10a 75 30 50 60 150 150 160 130 200 200 200 200 ns ns ns ns ns ns ns ns ns ns ns ns current monitor amp (pw-82520/82521n0) current monitor gain 0.40 v/a current monitor amp (pw-82520n3) current monitor gain 1.33 v/a current monitor amp (pw-82520n1) current monitor gain 4 v/a current command transconductance ratio pw-82520n1 pw-82520n3 pw-82520/82521n0 non-linearity temperature coefficient of g pw-82520n1/n3 pw-82520/82521n0 g tested using circuit shown in figure 7 io = 1a io = 3a io = 10a 0.24 0.73 2.37 -2.5 0.25 0.75 2.50 0.038 0.05 0.26 0.76 2.63 +2.5 a/v a/v a/v % fsr %fsr/c %fsr/c vbus+ s upply nominal operating voltage pw-82520n1/n3/n0 pw-82521n0 v n o m 18 36 28 56 70 140 vdc vdc i o c i o p i c l i o f f s e t r o n r c v f output (pw-82521n0) output current continuous output current pulsed current limit current offset output on-resistance output conductor resistance output conductor resistance temp coefficient diode forward voltage drop pulse width 50sec figure 7, v c m d = 0v +25c +125c +25c i d = 10a 12.0 -0.3 14.0 0 10 18 15.4 +0.3 0.100 0.170 0.080 330 1.9 a a a a ? ? ? ppm/c v
5 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 pwm in + peak voltage - peak voltage frequency, pw-82520n1/n3 frequency, pw-82520/82521n0 linearity error duty cycle vp+ vp- f p w m f p w m lin d.c. vcc = 4.5 - 5.5v vcc = 4.5 - 5.5v 2.3 -2.8 10 10 -2 49 2.5 -2.5 50 2.8 -2.3 110 55 +2 51 v v khz khz % % pwm out free run frequency pw-82520n1/n3 pw-82520/82521n0 stability, temperature f p w m full temp range 95 47.5 100 50 0.5 105 52.5 2.0 khz khz % h all signals ( ha, hb, hc) logic 0 logic 1 v i l v ih 3.5 1.5 vdc vdc enable enabled disabled v i l v ih 3.5 1.5 vdc vdc table 2. pw-82520/21n specifications ( continued) (unless ot h erwise specified , v bus = 28v dc , v d r = +15v, v c c = +5v, v d d = +5v, v e e = -5v, t c = 25c, l l = 500 h , pwm in = pwm out at ? f ree r unning freq uency) parameter symbol test conditions min typ max units sync in low high duty cycle sync range as % of free-run frequency input impedance v i l v ih d .c . r i n 3.5 49 110 50 10 1.5 51 vdc vdc % % k ? isolation case to ground 500 vdc hipot 10 m ? tac h out/ dir out output voltage imax v o l i o @ 1ma 0.4 10 vdc ma vdc v v/c +4 800 2 -4 v c m d command in+/- differential input input offset input offset drift vdc v/s s to 0.1% +5.8 3 1.4 -5.8 v o = 0.2 to 4.5v v c l a m p command out internal voltage clamp slew rate settling time th ermal ( pw-82520n1/n3/n0, pw-82521n0 ) thermal resistance junction-case case-air junction temperature case operating temperature case storage temperature j-c c-a tj t c t c s -55 -65 4 5.5 +150 +125 +150 c/w c/w c c c weight pw-82520n1/n3/n0, pw-82521n0 1.7 (48) oz (g) +5v s upply voltage current v c c i c c +4.5 +5.0 10 +5.5 15 vdc ma +5v to +15v s upply voltage current v d d i d d +15v +15v +4.5 35 +16.5 50 vdc ma -5v to -15v s upply voltage current v e e i e e -15v -15v -16.5 30 -4.5 50 vdc ma lead solder 10sec @300c +15v s upply voltage current disabled (pw-82520n1/n3/n0, pw-82521n0) enabled (pw-82520n1/n3/n0, pw-82521n0) v d r i d r i d r enable = high enable = low +13.5 +15.0 300 30 +16.5 40 vdc a ma
6 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 introduction the pw-82520/21n is a 3-phase high performance current con - trol (torque loop) motor controller hybrid, which provides true four-quadrant control through zero current (refer to figure 1. pw-82520/21n block diagram). its high pulse width modulation (pwm) switching frequency makes it suitable for operation with low inductance motors. the pw-82520/21n hybrids can accept single-ended or differential mode command signals. the current gain can be easily programmed to match the end user system requirements. the addition of an externally wired compensation network provides the user with optimum control of a wide range of loads. the pw-82520/21n uses single point current sense technology with an internal non-inductive hybrid sense resistor (rsense), which yields a highly linear current output over the full -55c to +125c military temperature range. the output current non-lin - earity is less than 1.5% and the total error due to all the factors such as offset, initial component accuracy, etc., is maintained well below 3% of the full-scale rated output current. the hall sensor interface for current commutation has built-in decoder logic that ignores illegal codes and ensures that there is no cross conduction. the hall sensor inputs are internally pulled up to +5v and they can be driven from open-collector outputs. the pwm frequency can be programmed externally by adding a capacitor from pwm out to pwm gnd. multiple pw-82520n's can be synchronized in two ways: 1) by using one device as a master and connecting its pwm out pin to the pwm in of all the other slave devices, or 2) by applying a master sync pulse from an external source to the pwm in pins on all devices to be synchronized. the enable input signal provides quick start and shutdown of the internal pwm. in addition, built-in under-voltage fault protec - tion turns off the output in case of improper power supply voltages. the hybrid features dual current limiting functions. the input command amplifier output is limited to 5v, limiting the motor current under normal operation. in addition, there is a cycle-by- cycle current limit which kicks in to protect the hybrid as well as the load (see table 2 for i c l limits). basic operation and advantages the pw-82520/21n uses a complementary four-quadrant drive technique to control current in the load. the complementary drive has the following advantages over standard drives: 1. holding torque in the motor at zero commanded current 2. linear current control through zero 3. no deadband at zero the complementary drive design produces a 50% pwm duty cycle in response to a zero current command. during a zero cur - rent command the benefit of a complementary 4 quadrant drive over a standard 4 quadrant is as follows: complementary (figu re s 2, 3a) complementary drives produce a bi-directional holding torque by driving a balanced bi-polar current into the motor that has an average value of zero. during the first quarter of the pwm cycle (starting at time zero on figure 3a) the mosfet's, phase a upper (ua) and phase b lower (lb) (figure 2), are turned on. this allows current flow from phase a to phase b to increase to +imax. during the second quarter of the pwm cycle, the first pair of transistors, ua and lb are turned off and a second pair phase a lower (la) & phase b upper (ub) (figure 2) are turned on. this allows the current in phase a & b from the previous quarter cycle to decrease from imax to zero. the average current during the first two-quarter cycles is positive. during the third quarter of the pwm cycle, the second pair of switches ub & la remain on allowing current to flow, in the negative direction, from phase b to phase a and increase to Cimax as shown in figure 3a. during the fourth quarter of the pwm cycle, the first pair of switches ua & lb are turned on while the second pair of switch - es ub & la are turned off, to allow the current in the inductor to decrease to zero. the average current in the phases for the third and fourth quarter cycles is negative. the positive current (phase a to b) in the first two-quarter cycles produces a torque in one direction and the negative current (phase b to a) in the third and fourth quarter cycles produces a torque in the opposite direction. the average of the two opposing torques results in a net zero or holding torque. v bu s phase a upper phase a lo wer phase b upper phase b lo wer rsense phase a phase b phase c - + off off on on figure 2. complementary 4- q uadrant drive first h alf of pwm cycle
7 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 ua la ub lb 0 dr iv e switches and phase current vs . time on off on off on off on off switches phase current time (half phase) 1 2 3 4 figure 3b. standard 4- q uadrant drive pwm cycle ua la ub lb 0 dr iv e switches and phase current vs . time on off on off on off on off phase current switches time (quar ter phase) 12 3 4 1 2 3 4 figure 3a. complementary 4- q uadrant drive pwm cycle n on-complementary (figure s 2, 3b) non-complementary drives produce a unidirectional torque by applying a unipolar current into the motor that has an average positive value as shown in figure 3b. during the first half of the pwm cycle the mosfet's, phase a upper and phase b lower, are turned on to provide current into the phases. during the second half of the pwm cycle the drive is in dead time, all transistors are turned off, the motor current continues to flow in the same direction through the device diodes, until it decays to zero. current flowing in to and out of the phases produces a net torque in one direction. major a dvantages the advantage of a complementary 4-quadrant drive over a standard 4-quadrant drive is that it provides holding torque dur - ing a zero current command. the motor current at 50% duty cycle is simply the magnetizing current of the motor winding. using the complementary 4-quadrant technique allows the motor direction to be defined by the duty cycle. relative to a given switch pair, i.e. phase a upper and phase b lower, a duty cycle greater than 50% will result in a clockwise rotation whereas a duty cycle less than 50% will result in a coun - ter clockwise rotation. therefore, with the use of average current mode control, direction can be controlled without the use of a direction bit and the current can be controlled through zero in a very precise and linear fashion. the pw-82520n contains all the circuitry required to close an average current mode control loop around a complementary 4- quadrant drive. the pw-82520n use of average current mode control simplifies the control loop by eliminating the need for slope compensation and by eliminating the pole created by the motor inductance. slope compensation and the pole created by the motor inductance are two limitations normally associated with implementing standard 4 quadrant current mode controls. functional pin descriptions vbus+a, vbus+b, vbus+c the vbus+ supply is the power source for the motor phases. for the pw-82520 (pw-82521) series device, the normal operating voltage is 28vdc (100vdc) and may vary from +18 (+36) to +70vdc (+140vdc) with respect to vbus-. the power-stage mosfets in the hybrid have an absolute maximum vbus+ sup - ply voltage rating of 100v (200v). the user must supply sufficient external capacitance or circuitry to prevent the bus supply from exceeding the maximum recommended voltages at the hybrid power terminals under any condition. p ower-on seq uence ( i mportant! ) the vbus+ should be applied at least 50ms after v d d and v e e to allow the internal analog circuitry to stabilize. if this is not pos - sible, the hybrid must be powered up in the "disabled" mode. vbus- this is the high current ground return for vbus+. this point must be closely connected to supply gnd for proper operation of the current loop. vcc (+5v s upply) and vcc rtn
8 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 these are logic signals from the motor hall-effect sensors. they use a phasing convention referred to as 120 degree spacing; that is, the output of ha is in phase with motor back emf voltage vab, hb is in phase vbc, and hc is in phase with vca. logic 1 (or high ) is defined by an input greater than 3.5vdc or an open circuit to the controller; logic 0(or low) is defined as any hall voltage input less than 1.5vdc. internal to the pw-82520/21n are 10k pull-up resistors tied to +5vdc on each hall input. the pw-82520/21n will alternately operate with hall phasing of 60 electrical spacing. if 60 commutation is used, then the out - put of hc must be inverted as shown in figures 4 and 5. figure 4 illustrates the hall sensor outputs along with the cor - responding back emf voltage they are in phase with. hall inpu t signal conditioning when the motor is located more than two feet away from the pw-82520/21n controller or is in a noisy electrical environment the hall inputs require filtering from noise. it is recommended to use a 100 ? resistor in series with the hall signal and a 2000 pf capacitor from the hall input pin to the hall supply ground pin as shown in figures 6 and 7. phase a, b, c these inputs are used to power the digital circuitry of the hybrid. vdr (+15v s upply) this input is used to power the gate driver circuitry for the output mosfets. there is no power consumption from v d r when the hybrid is disabled. v dd (+5v to +15v s upply ), v ee (-5v to -15v s upply ) these inputs can vary from 5v to 15v as long as they are symmetrical. v d d and v e e are used to power the small signal analog circuitry of the hybrid. please note that using 5v supply will reduce the quiescent power consumption by approximately 60% when compared to 15v operation. supply gnd this pin is the return for the v d r , v e e and v d d supplies. the phase current sensing technique of the pw-82520n/21n requires that vbus- and supply gnd (see figures 6 and 7) be con - nected together externally (see vbus- supply). case gnd this pin is internally connected to the hybrid case. in some applica - tions the user may want to tie this to ground for emi consider - ations. hall a, b, c signals hall-effect sensor phasing vs. mot or back emf for cw rot a tion (120 commutations) 300 0 60 120 180 240 300 360 /0 60 v ab v bc v ca back emf of mot or rot a ting cw cw ha hb hc hc in phase with v ab in phase with v bc in phase with v ca in phase with v ac (60?) figure 4. hall phasing s hc ha 120 n hb 120 n hc 120 remote position sensor (hall) sp acing for 120 degree commut a tion 60 60 remote position sensor (hall) sp acing for 60 degree commut a tion s ha hb hc figure 5. hall sensor spacing
9 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 phase a phase a phase b phase c vbus- phase b vbus+ c phase c hall c hall b hall a r4 r3 r2 100 100 100 c3 2000pf c4 2000pf c5 2000pf ha hb hc case gnd pwm in pwm out +5v to +15v suppl y gnd -5v to -15v command gnd command in - command in + error amp out command out error amp input current monit or out enable c6 c7 10k 10k r1 r5 + + + gnd +28v mot or bldc pw-82520/21n v dd gnd v ee command signal enable - - - optional current monit or out cext + + v dr v cc +5v supply +15v supply +15v vbus+ b vbus+ a { { { { { { { c1 sync in figure 6. voltage control hook-up phase a vbus- phase b vbus+ b phase c hall c hall b hall a case gnd pwm in pwm out +5v supply suppl y gnd +15v supply command gnd command in - command in + error amp out command out error amp input current monit or out enable c6 c7 10k, 0.5% 10k r2a 10k, 0.5% r2b 1meg r7 c1 4700pf r1 + + + pw-82520/21n v dd gnd v ee command signal enable - - - optional cext + + v dr v cc +5v to +15v -5v to -15v vbus+ c vbus+ a phase a phase b phase c r4 r3 r2 100 100 100 c3 2000pf c4 2000pf c5 2000pf ha hb hc gnd +28v mot or bldc +15v tach dir 10k 10k tach out dir out { { { { { { { c1 sync in figure 7. tor q ue (current) control hook-up
10 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 this input, as shown in figure 9, is used to synchronize the pwm switching frequency with an external clocking device. the pwm switching frequency can be pulled to up-to 20% faster than its free running frequency. pwm in the pwm comparator inputs are used to control the pwm pulse width. pwm out or an external triangular waveform is connected to this pin. warning: never apply power to the hybrid without connecting either pwm out or an external triangular waveform to pwm in! failure to do so may result in one or more outputs latching on. pwm fre quency the pwm frequency from the pw-82520n1/n3 (pw-82520n0/21n0) pwm out pin will free-run at a frequency of 100khz 5khz (50khz 2.5khz). the pwm frequency is user adjustable from 100khz (50khz) down to 10khz through the addition of an external capacitor. the pwm triangular wave - form generated internally is brought out to the pwm out pin. this output, or an external triangular waveform generated by the user, may be connected to pwm in on the hybrid. pwm out this is the output of the internally generated pwm triangle wave - form. it is normally connected to pwm in. the frequency of this output may be lowered by connecting an npo capacitor (c e x t ) between pwm out and command gnd. the pwm frequency is determined by the following formula: 33.0e-6 330pf + c ext pf pw -82520n1/n3: 16.5e-6 330pf + c ext pf pw -82520/21n0: error amp input , error amp out these are the input and output pins for the error amplifier and are used for compensation. sync period 0v 5v 50% duty cycle figure 9. sync input signal these are the power drive outputs to the motor and switch between vbus+ input and vbus- input or become high imped - ance (see table 3). enable the enable input is an active low (l) logic signal that enables or disables the internal pwm. in the disable mode (h), the pwm is shut down and the outputs, phase a, phase b and phase c, are in an "off" state and no voltage is applied to the motor. tach out the tach out provides a tachometer signal that is a square wave with a frequency relative to motor speed and is derived from the three hall inputs ha, hb, hc. the tachometer circuitry combines these three signals into a single pulse train as a 50%-duty-cycle pulse. there are three pulses that occur every 360 electrical degree. the number of pulses per motor revolution is formulated below: tf x 60 pr pr = x 3 (e .g., 6 pulses/re v olution f or a 4 pole motor) p 2 rpm = p = number of motor poles pr = number of pulses per re v olution tf = t ach output frequency cycles/second the motor rpm is: where: dir out the dir out indicates the direction the motor is rotating, clock - wise (cw) for a lo, or counterclockwise (ccw), indicated as a logic hi. current monitor out this is a bipolar analog output voltage representative of motor current. the current monitor out will have the same scal - ing as the command in inputs. sync in external pi regulator 10.0 k r1 4700 pf c1 1 meg error amp input command out current monitor out r2a 10.0 k r2 b 10.0 k - + o error amp out 470 pf r7 100 figure 8. standard pi current loop
11 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 compens ation the pi regulator in the pw-82520/21n can be tuned to a spe - cific load for optimum performance. figure 8 shows the stan - dard current loop configuration and tuning components. by adjusting r1, r2 and c1, the amplifier can be tuned. the value of r1, c1 will vary, depending on the loop bandwidth require - ment. command in+, command in- , command g round , c ommand out these are the connection pins for the command amplifier. the command amplifier has a differential input that operates from a 4vdc full-scale analog current command. the command ampli - fier output signal is internally limited to approximately 5vdc to prevent the amplifier from saturating. the input impedance of the command amplifier is 50k ? . the pw-82520/21n can be used either as a current or voltage mode controller. when used as a torque controller (current mode), the input command signal is processed through the com - mand buffer, which is internally limited to 5vdc. the output of the buffer (command out) is summed with the current monitor output into the error amplifier. external compensation is used on the error amp, so the response time can be adjusted to meet the application. when used in the voltage mode, the voltage command signal is applied to the command amplifier, to control the voltage applied to the motor. the command amplifier output is coupled into the error amplifier. the error amplifier directly varies the pwm duty cycle to control the voltage applied to the motor phase. the nominal pwm frequency in the voltage mode is 50% with zero volts applied to the command input. the pwm duty cycle is var - ied by the voltage applied to the command input according to the transfer function, 12% per volt applied to the command input. the duty cycle range of the output voltage is limited to approximately 5-95% in both current and voltage modes. command gnd this pin is used when the command buffer is used single-ended and the command in- or command in+ is tied to command gnd. transconduc tance ratio and offset when the pw-82520/21n is used in the current mode, the com - mand inputs (command in+ and command in-) are designed such that 4vdc on either input, with the other input connected to ground will result in full-scale current (continuous output current: (ioc) - refer to table 2) flow into the load. the dc cur - rent transfer ratio accuracy is 5% of the rated current including offset and initial component accuracy. the initial output dc cur - rent offset with both command in+ and command in- tied to the ground will be as shown in table 2 (ioffset) when measured using a load of 0.5mh and 1.0w at ambient room temperature with standard current loop compensation (see figure 8). the winding phase current error shall be within the cumulative limits of the transconductance ratio error and the offset error. r s + rs+ is the high side of the sense resistor used for non-scaled test purposes only. accuracy is not a guaranteed parameter. output current output current derating as a function of the hybrid case tempera - ture is provided in figures 11 and 12. the hybrid contains internal pulse by pulse current limit circuitry to limit the output current during fault conditions (see table 2). current limit accuracy is +10/-15%. warning! the pw-82520/(21)n does not have short cir - cuit protection. the pw-82520/(21)n must see a minimum of 100h (400h) inductive load phase-to-phase or enough phase-to-phase line-to-line resistance to limit the continuous output current to less than ioc at all times. operation into a short or a condition that requires excessive output current will damage the hybrid. table 4. h all inputs for h -bridge controller inputs outputs enable command in ha hb hc ph b ph c ph a l positive 1 1 0 z l h l negative 1 1 0 z h l h - 1 1 0 z z z table 3. commutation trut h table inputs outputs enable command in hall b c a l pos 1 0 1 l h z l pos 1 0 0 l z h l pos 1 1 0 z l h l pos 0 1 0 h l z l pos 0 1 1 h z l l pos 0 0 1 z h l l neg 0 0 1 z l h l neg 0 1 1 l z h l neg 0 1 0 l h z l neg 1 1 0 z h l l neg 1 0 0 h z l l neg 1 0 1 h l z h - - - - z z z 1=logic voltage >3.5vdc, 0=logic voltage < 1.5vdc * direction is based on the convention shown in figure 4. actual motor set up might be different. a b c phase dir cw cw cw cw cw cw ccw ccw ccw ccw ccw ccw - polarity dir out l l l l l l h h h h h h x
12 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 phase a phase a phase c vbus- phase b vbus+ b phase c hall c hall b hall a c1 gnd +28v + +5v +5v vbus+ c vbus+ a { { { { { { figure 10. brus h motor hook-up -50 -25 02 55 07 5 100 125 0 2 4 6 8 10 12 pw -82521n0 amps case te mperature (?c) (vbus+ = 100v) (hsw = 20khz) -50 -25 02 55 07 5 100 125 0 2 4 6 8 10 12 pw -82520n0 amps case te mperature (?c) (vbus+ = 28v) figure 11. output current for continuous commutation (electrical > 600rpm, pwm = 50k hz) th ermal operation it is necessary that the base (heat sink surface - figure 13) of the pw-82520/21n be mounted to a heat sink. this heat sink shall have the capacity to dissipate heat generated by the hybrid at all levels of current output, up to the peak limit, while maintain - ing the case temperature limit as per figure 11. brus h motor operation the pw-82520/21n can also be used as a brush motor controller for current or voltage control in an h-bridge configuration. the pw-82520/21n would be connected as shown in figure 10. all other connections are as shown in either figures 6 or 7 depending on voltage or current mode operation. the hall inputs are wired per table 4. a positive input command will result in positive current to the motor out of phase a. optional features external sensing r esistor an external sense resistor can be connected to replace the inter - nal resistor if this option is required. please contact factory for this option.
13 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 pw-82520/21n p ower d issipation there are two major contributors to power dissipation in the motor driver: conduction losses, and switching losses. an example calculation is shown below: vbus = +28 v (bus voltage) i o a = 3 a, i o b = 7 a (see figure 12) f pwm = 25 khz (switching frequency) ton = 36 s, t = 40 s (90% duty cycle) (see figure 12) ron = 0.055 ? (on-resistance, see table 2) rc = 0.080 ? (conductor resistance, see table 2) ts1 = tf = 200 ns, ts2 = 2tr = 400 ns (see table 2, figure 12) i motor rms = i ob i oa + (i ob - i oa ) 3 2 ( ) ton t ( ) i motor rms = 7 x 3 + (7 - 3) 3 2 ( ) 36 40 ( ) i motor rms = 4.87 amps 1. t ransistor c onduction losses (p t ) p t = (imotor rms) 2 x (ron) p t = (4.87) 2 x (0.055) p t = 1.30 watts 2. s witching losses (p s ) t i ob t on i oa vbus i o t s2 t s1 figure 12. output ch aracteristics ps = [ vbus ( i o a (ts1) + i o b (ts2) ) fo] / 2 ps = [ 28 ( 3 (200 x10 -9 ) + 7 (400 x10 -9 ) ) 25x10 3 ] / 2 ps = 1.19 watts transis tor po wer diss ipation ( p q ) pq = p t + p s pq = 1.30 + 1.19 = 2.49 watts output conduc tor diss ipation p c = (imotor rms) 2 x (rc) p c = (4.87) 2 x (0.080) p c = 1.90 watts 3. transistor power dissipation for continuous commutation (e lectrical > 600rpm) pqc = pq (0.33) pqc = (2.49) x (0.33) pqc = 0.82 watts 4. total hybrid power dissipation p t o t a l = (pq + pc) x 2 p t o t a l = (2.49 + 1.90) x 2 p t o t a l = 8.78 watts
14 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 phase b function pin function 1 vbus+ a 41 tach out 2 vbus+ a 40 dir out 3 phase a 39 hall b 4 phase a 38 hall a 5 vbus+ b 37 hall c 6 vbus+ b 36 enable 7 phase b 35 v c c 8 34 v c c rtn 9 vbus- 33 v d r 10 vbus- 32 sync in 11 rs+ 31 v d d 12 rs+ 30 supply gnd 13 vbus+ c 29 v e e 14 vbus+ c 28 n/c 15 phase c 27 n/c 16 phase c 26 current monitor out 25 error amp in 24 error amp out 23 command out 22 command in - 21 command in + 20 command gnd 19 pwm out 18 pwm in 17 case gnd table 5. pw-82520/21n pin functions pin 1.400 0.005 (35.58 0.127) 1.150 0.005 (29.21 0.127) pin no .1 contrasting color bead 0.100 0.005 typ (2.54 0.127) 24 eq. sp . @ 0.100 = 2.400 0.010 (@ 2.54 = 60.96 0.254) 2.600 0.005 (66.04 0.127) 0.150 0.005 typ (3.81 0.127) 15 eq. sp . @ 0.150 = 2.250 0.010 (@ 3.81 = 57.15 0.254) 0.250 max (6.35) 0.250 0.010 (6.35 0.254) 0.030 0.002 dia typ (0.762 0.051) 0.018 0.002 dia typ (0.457 0.051) bo tt om view side view no tes: 1. dimensions in inches (mm) . 2. lead identifica tion numbers are for reference on ly. 41 1 17 16 heat sink surf ace figure 13. mec h anical outline
15 data device corporation www.ddc-web.com pw-82520/21n k-8/08-0 ordering information pw-8252xnx- x x 0 reliability grade: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature range: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data rating: 1 = 1a 3 = 3a 0 = 10a voltage 0 = 100v 1 = 200v (available with n0 rating only) *standard ddc processing with burn-in and full temperature test see table below. these products contain tin-lead solder finish as applicable to solder dip requirements. notes: 1. for process requirement b* (refer to ordering information), devices may be non-compliant with mil-std-883, test method 1015, paragraph 3.2. contact factory for details. 2. when applicable. standard ddc proce ssing for hybrid and monolit h ic hermetic products mil-std-883 test method(s) condition(s) inspection 2009, 2010, 2017, and 2032 seal 1014 a and c temperature cycle 1010 c constant acceleration 2001 3000g burn-in 10 1 5 , (note 1) 103 0 (note 2) table 1
d a t a device corpora tion registered t o iso 9001:2000 file n o . a5976 r e g i s t e r e d f i r m ? u 16 k-8/08-0 printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. 105 wilbur place, bohemia, new york, u.s.a. 11716-2426 for technical support - 1-800-ddc-5757 ext. 7771 h eadquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)89-150012-11, fax: +49-(0)89-150012-22 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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